module counter_tb;

    reg clk = 0, rst = 0;
    wire [7:0] cnt;

    initial begin
        #17 rst = 1;
        #19 rst = 0;
        #29 rst = 1;
        #11 rst = 0;
        #100 $stop;
    end

    always #5 clk = !clk;

    counter counter_inst (
        .clk        (clk),
        .rst        (rst),
        .cnt        (cnt)
    );

    initial begin
        $monitor("At time %t, value = %h (%0d)", $time, cnt, cnt);
    end

endmodule